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| KBE00F005A-D411 MCP MEMORY MCP Specification 512Mb NAND*2 + 256Mb Mobile SDRAM*2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 Revision 1.0 June 2005 KBE00F005A-D411 Document Title MCP MEMORY Multi-Chip Package MEMORY 512M Bit(64Mx8) Nand Flash*2 / 256M Bit (2Mx32x4Banks) Mobile SDRAM*2 Revision History Revision No. History 0.0 Initial issue. - 1Gb NAND Flash DDP B-Die _ Ver 0.1 - 512Mb Mobile SDRAM DDP F-Die _ Ver 1.0 Draft Date April 06, 2005 Remark Preliminary 1.0 June 21, 2005 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 2 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Multi-Chip Package MEMORY 512M Bit(64Mx8) Nand Flash*2 / 256M Bit (2Mx32x4Banks) Mobile SDRAM*2 FEATURES Address configuration Organization 16M x 32 Bank BA0, BA1 Row A0 - A12 Column Address A0 - A7 GENERAL DESCRIPTION The KBE00F005A is a Multi Chip Package Memory which combines 1Gbit Nand Flash Memory(organized with two pieces of 512Mbit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 1Gbit NAND Flash memory is organized as 128M x8 bits and 512Mbit Mobile SDRAM is organized as 4M x32 bits x4 banks In 1Gbit NAND Flash,its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typically 200s on the 528-byte page and an erase operation can be performed in typically 2ms on a 16Kbyte block. Data in the data register can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The KBE00F005A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type. 3 Revision 1.0 June 2005 KBE00F005A-D411 PIN CONFIGURATION MCP MEMORY 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 DNU DNU DNU NC NC RE CLE Vcc CE WEn Vdd Vss NC Vss A4 WP ALE Vss R/B DQ31 DQ30 Vddq Vssq Vdd A5 A7 A9 DQ25 DQ27 DQ29 DQ28 Vssq Vddq A6 A8 CKE DQ18 NC DQ22 DQM3 DQ26 Vddq Vssq A12 A11 CS1 DQ17 DQ19 DQ24 DQ23 DQM2 Vssq Vddq NC RAS DQ15 DQ16 NC DQM1 DQ9 CLK Vddq Vssq Vdd CAS DQ20 DQ21 DQ13 DQ12 NC NC Vss Vdd Vss CS BA0 DQ14 DQ11 DQ10 NC DQM0 Vssq Vddq WEd BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 Vddq Vssq A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 Vddq Vssq Vdd Vss NC NC IO3 IO5 NC IO7 Vssq Vddq N P IO0 IO1 IO2 NC Vcc IO6 NC NC Vddq Vssq NC NC NC NC NC Vss IO4 Vdd Vss NC R DNU DNU DNU DNU 137 FBGA: Top View (Ball Down) NAND M-SDR 4 Revision 1.0 June 2005 KBE00F005A-D411 PIN DESCRIPTION Pin Name CLK CKE CS,CS1 RAS CAS WEd A0 ~ A12 BA0 ~ BA1 DQM0 ~ DQM3 DQ0 ~ DQ31 Vdd Vddq Vss Vssq Pin Function(Mobile SDRAM) System Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Input Bank Address Input Input/Output Data Mask Data Input/Output Power Supply Data Out Power Ground DQ Ground Pin Name NC DNU Do Not Use Pin Name CE RE WP WEn ALE CLE R/B IO0 ~ IO7 Vcc Vss MCP MEMORY Pin Function(NAND Flash) Chip Enable Read Enable Write Protection Write Enable Address Latch Enable Command Latch Enable Ready/Busy Output Data Input/Output Power Supply Ground Pin Function No Connection ORDERING INFORMATION KB E Samsung MCP Memory(4chips) Device Type NAND + NAND + SDRAM+SDRAM NOR Flash Density, Voltage, Organization, Bank Size, Boot Block 00 = None 00 F 0 0 5 A - D 411 Access Time 411 : NAND Flash 50ns NAND Flash 50ns Mobile SDRAM 9ns Mobile SDRAM 9ns Package D = FBGA(Lead-Free) NAND Flash Density, Voltage, Organization F = 512M+512M, 2.7V/2.7V, x8 UtRAM Density, Voltage, Organization 0 = None SRAM Density, Voltage, Organization 0 = None Version A = 2nd Generation SDRAM Interface, Density, Voltage, Organization, Option 5 = M-SDR, 256M+256M, 1.8V/1.8V, x32 NOTE : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. 5 Revision 1.0 June 2005 KBE00F005A-D411 FUNCTIONAL BLOCK DIAGRAM MCP MEMORY Vcc Vss CE RE WP WEn ALE CLE R/B 1Gb NAND Flash Memory IO0 to IO7 Vdd Vddq Vss Vssq CLK CKE CS CS1 RAS CAS WEd A0~A12 BA0~BA1 DQM0~DQM3 512Mb Mobile SDRAM DQ0 to DQ31 6 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY 1Gb(128Mb x 8) NAND Flash DDP B-Die 7 Revision 1.0 June 2005 KBE00F005A-D411 PIN DESCRIPTION Pin Name I/O0 ~ I/O7 Pin Function MCP MEMORY DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to 'Page read' section of Device operation . READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. OUTPUT BUFFER POWER VccQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected. DO NOT USE Leave it disconnected. CLE ALE CE RE WE WP R/B VccQ Vcc Vss N.C DNU NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 8 Revision 1.0 June 2005 KBE00F005A-D411 Figure 1. Functional Block Diagram VCC VSS A9 - A26 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders MCP MEMORY 1,024M + 32M Bit NAND Flash ARRAY (512 + 16)Byte x 262,144 Page Register & S/A A0 - A7 A8 Command Command Register Y-Gating I/O Buffers & Latches VCC VSS Output Driver I/0 0 I/0 7 CE RE WE Control Logic & High Voltage Generator Global Buffers CLE ALE WP Figure 2. Array Organization 1 Block = 32 Pages (16K + 512) Byte 256K Pages (=8,192 Blocks) 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 B x 32 Pages = (16K + 512) Bytes 1 Device = 528B x 32Pages x 8,192 Blocks = 1,056 Mbits 8 bit 16 Bytes 512B Bytes Page Register 512 Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 A26 I/O 2 A2 A11 A19 *L 16 Bytes I/O 3 A3 A12 A20 *L I/O 0 ~ I/O 7 I/O 4 A4 A13 A21 *L I/O 5 A5 A14 A22 *L I/O 6 A6 A15 A23 *L I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address) NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". 9 Revision 1.0 June 2005 KBE00F005A-D411 Product Introduction MCP MEMORY This device is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on this device. This device has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space requires 27 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of this device. The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 byte structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased. Table 1. Command Sets Function Read 1 Read 2 Read ID Reset Page Program (True)(2) Page Program (Dummy)(2) Copy-Back Program(True)(2) Copy-Back Program(Dummy)(2) Block Erase Multi-Plane Block Erase Read Status Read Multi-Plane Status 1st. Cycle 00h/01h(1) 50h 90h FFh 80h 80h 00h 03h 60h 60h---60h 70h 71h(3) 2nd. Cycle 10h 11h 8Ah 8Ah D0h D0h 3rd. Cycle 10h 11h O O O Acceptable Command during Busy NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation. Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation. 3. The 71h command should be used for read status of Multi Plane operation. 4. Multi plane operation and Copy-Back Program are not supported with 1.8V device. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 10 Revision 1.0 June 2005 KBE00F005A-D411 Memory Map MCP MEMORY The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited. Figure 3. Memory Array Map Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block) Block 0 Page 0 Page 1 Block 1 Page 0 Page 1 Block 2 Page 0 Page 1 Block 3 Page 0 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 4092 Page 0 Page 1 Block 4093 Page 0 Page 1 Block 4094 Page 0 Page 1 Block 4095 Page 0 Page 1 Page 30 Page 31 Page 30 Page 31 528byte Page Registers Page 30 Page 31 528byte Page Registers Page 30 Page 31 528byte Page Registers 528byte Page Registers Plane 4 (1024 Block) Plane 5 (1024 Block) Plane 6 (1024 Block) Plane 7 (1024 Block) Block 4096 Page 0 Page 1 Block 4097 Page 0 Page 1 Block 4098 Page 0 Page 1 Block 4099 Page 0 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 8188 Page 0 Page 1 Block 8189 Page 0 Page 1 Block 8190 Page 0 Page 1 Block 8191 Page 0 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 528byte Page Registers 528byte Page Registers 528byte Page Registers 528byte Page Registers 11 Revision 1.0 June 2005 KBE00F005A-D411 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Current Symbol VIN/OUT VCC VCCQ TBIAS TSTG Ios MCP MEMORY Rating -0.6 to + 4.6 -0.6 to + 4.6 -0.6 to + 4.6 -40 to +125 -65 to +150 5 Unit V C C mA NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND , TA=-25 to 85C) Parameter Supply Voltage Supply Voltage Supply Voltage Symbol VCC VCCQ VSS Value Min 2.5 2.5 0 Typ. 2.7 2.7 0 Max 2.9 2.9 0 Unit V V V 12 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Value Min CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) I/O pins VCCQ -0.4 VCC -0.4 IOH-100A IOH=100A VOL=0.1V -0.3 VCCQ -0.4 3 Typ 10 10 10 10 4 Max 20 20 20 1 50 10 10 VCCQ +0.3 VCC +0.3 0.5 0.4 mA A mA DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO Test Conditions tRC=50ns, CE=VIL IOUT=0mA Unit Operating Current Input High Voltage VIH* Except I/O pins Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) VIL* VOH VOL IOL(R/B) V NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less Valid Block Parameter Valid Block Number Symbol NVB Min 8,052 Typ. Max 8,192 Unit Blocks NOTE : 1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for an appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. 3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. 13 Revision 1.0 June 2005 KBE00F005A-D411 AC TEST CONDITION (TA=-25 to 85C , Vcc=2.5V~2.9V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (VccQ:2.7V +/-10%) MCP MEMORY Value 0V to VccQ 5ns VccQ/2 1 TTL GATE and CL=30pF Capacitance(TA=25C, VCC=2.7V , f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 20 20 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE H L H L L L X X X X X ALE L H L H L L X X X X (1) CE L L L L L L X X X X H WE RE H H H H H WP X X H H H X X H H L Read Mode Write Mode Data Input Data Output During Read(Busy) on the devices During Program(Busy) During Erase(Busy) Write Protect Mode Command Input Address Input(4clock) Command Input Address Input(4clock) H X X X X X H X X X X X 0V/VCC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG(1) tDBSY Nop tBERS Min Typ 200 1 2 Max 500 10 1 2 3 Unit s s cycle cycles ms NOTE : 1.Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25'C 14 Revision 1.0 June 2005 KBE00F005A-D411 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25(1) 0 10 20 10 50 15 Max .- MCP MEMORY Unit ns ns ns ns ns ns ns ns ns ns ns NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE or CE High to Output hold RE High Hold Time Output Hi-Z to RE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tOH tREH tIR tWHR tRST Min 10 10 20 25 50 15 15 0 60 Max 15 100 30 45 30 20 5/10/500(1) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns s NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. TBD means "To Be Determinded". 15 Revision 1.0 June 2005 KBE00F005A-D411 NAND Flash Technical Notes Initial Invalid Block(s) MCP MEMORY Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) Initial Invalid Block(s) Table No * Check "FFh" ? Yes Check "FFh" at the column address 517 of the 1st and 2nd page in the block No Last Block ? Yes End Figure 4. Flow chart to create initial invalid block table. 16 Revision 1.0 June 2005 KBE00F005A-D411 NAND Flash Technical Notes (Continued) Error in write or read operation MCP MEMORY Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure ratein the qualification report does not include those reclaimed blocks. Failure Mode Write Read Erase Failure Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? No Program Error * Yes Program Completed * 17 : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Revision 1.0 June 2005 KBE00F005A-D411 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register MCP MEMORY Read Flow Chart Start Write 00h Write Address Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed No Reclaim the Error No Verify ECC Yes Page Read Completed Erase Error * * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement Buffer memory error occurs Page a Block A When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.) Block B 18 Revision 1.0 June 2005 KBE00F005A-D411 Pointer Operation MCP MEMORY Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from 'B' area, '01h' command must be inputted right before '80h' command is written. Table 2. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C) "A" area (00h plane) 256 Byte "B" area (01h plane) 256 Byte "C" area (50h plane) 16 Byte "A" "B" "C" Internal Page Register Pointer select commnad (00h, 01h, 50h) Pointer Figure 5. Block Diagram of Pointer Operation (1) Command input sequence for programming 'A' area The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h 'A','B','C' area can be programmed. It depends on how many data are inputted. '00h' command can be omitted. (2) Command input sequence for programming 'B' area The address pointer is set to 'B' area(256~511), and will be reset to 'A' area after every program operation is executed. Address / Data input 01h 80h 10h 01h 80h Address / Data input 10h 'B', 'C' area can be programmed. It depends on how many data are inputted. '01h' command must be rewritten before every program operation (3) Command input sequence for programming 'C' area The address pointer is set to 'C' area(512~527), and sustained Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h Only 'C' area can be programmed. '50h' command can be omitted. 19 Revision 1.0 June 2005 KBE00F005A-D411 System Interface Using CE don't-care. MCP MEMORY For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption. Figure 6. Program Operation with CE don't-care. CLE CE don't-care CE WE ALE 80h Start Add.(4Cycle) I/OX Data Input Data Input 10h tCS CE tCH CE tCEA tWP WE RE tREA I/OX out Figure 7. Read Operation with CE don't-care. CLE CE don't-care CE RE ALE R/B tR WE I/OX 00h Start Add.(4Cycle) Data Output(sequential) 20 Revision 1.0 June 2005 KBE00F005A-D411 I/O I/Ox I/O 0 ~ I/O 7 MCP MEMORY DATA Data In/Out ~528byte Command Latch Cycle CLE tCLS tCS CE tCLH tCH tWP WE tALS ALE tDS I/O0~7 tALH tDH Command Address Latch Cycle tCLS CLE tCS CE tWC tWC tWC tWP WE tALS ALE tDS I/O0~7 tDH tWH tALH tALS tWP tWH tALH tALS tWP tWH tALH tALS tWP tALH tDS tDH tDS tDH tDS tDH A0~A7 A9~A16 A17~A24 A25,,A26 21 Revision 1.0 June 2005 KBE00F005A-D411 Input Data Latch Cycle tCLH CLE MCP MEMORY tCH CE tALS ALE tWC WE tDS I/O0~7 tWH tDH tDS tDH tWP tWP tWP tDH tDS DIN 0 DIN 1 DIN 511 Serial access Cycle after Read(CLE=L, WE=H, ALE=L) CE tREA RE tRC tREH tCHZ* tREA tOH tREA tRHZ* I/Ox tRR R/B Dout Dout tRHZ* tOH Dout NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 22 Revision 1.0 June 2005 KBE00F005A-D411 Status Read Cycle tCLR CLE tCLS tCS CE tCH tCEA tWHR RE tDS I/OX 70h tDH tIR tREA tCLH MCP MEMORY tWP WE tCHZ tOH tRHZ tOH Status Output Read1 Operation(Read One Page) CLE CE tWC WE tWB tAR2 ALE tR RE tRR I/O0~7 00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Dout N Dout N+1 Dout N+2 tCHZ tOH tRC tRHZ tOH Dout 527 Column Address Page(Row) Address Busy R/B 23 Revision 1.0 June 2005 KBE00F005A-D411 Read1 Operation(Intercepted by CE) CLE MCP MEMORY CE WE tWB tAR ALE tR RE tRR I/O0~7 00h or 01h tCHZ tRC A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Dout N Dout N+1 Dout N+2 Column Address Page(Row) Address Busy R/B Read2 Operation(Read One Page) CLE CE WE tWB ALE tR tAR tRR RE I/O0~7 50h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Dout 511+M Dout 527 R/B M Address A0~A3 : Valid Address A4~A7 : Dont care Selected Row 512 16 Start address M 24 Revision 1.0 June 2005 KBE00F005A-D411 Page Program Operation MCP MEMORY CLE CE WE tWB ALE tPROG RE Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input I/O0~7 80h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Page(Row) Address tWC tWC tWC 70h Read Status Command I/O0 Sequential Data Column Input Command Address tWC tWB tBERS 60h A9 ~ A16 A17 ~ A24 A25,A26 Page(Row) Address DOh 70h R/B I/O0=0 Successful Program I/O0=1 Error in Program BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE CE WE ALE RE I/O0~7 I/O 0 R/B Auto Block Erase Setup Command Erase Command Busy Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase 25 Revision 1.0 June 2005 Multi-Plane Page Program Operation CLE CE tWC WE tWB tDBSY tWB KBE00F005A-D411 tPROG ALE RE I/O0~7 A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Column Address 80h Din N 80h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 Din 527 Din N Din 527 71h 10h Program Confirm Command (True) I/O Sequential Data Input Command Page(Row) Address Max. three times repeatable 11h Program 1 up to 528 Byte Data Command (Dummy) Serial Input Read Multi-Plane Status Command Last Plane Input & Program tDBSY : typ. 1us max. 10us Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7 R/B I/O0~7 80h A0 ~ A7 & A9 ~ A26 528 Byte Data 11h Address & Data Input 80h tDBSY 26 tDBSY Address & Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 11h 80h Address & Data Input R/B tDBSY tPROG 11h A0 ~ A7 & A9 ~ A26 528 Byte Data 80h Address & Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data MCP MEMORY 10h 71h Revision 1.0 June 2005 KBE00F005A-D411 Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 MCP MEMORY CLE CE tWC WE tWB ALE tBERS RE I/O0~7 60h A9 ~ A16 A17 ~ A24 A25,A26 Page(Row) Address DOh 71h I/O 0 Block Erase Setup Command Erase Confirm Command Read Multi-Plane Status Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation R/B I/O0~7 60h Address A9 ~ A26 60h Address 60h Address 60h Address D0h R/B Busy tBERS 71h 27 Revision 1.0 June 2005 KBE00F005A-D411 Read ID Operation MCP MEMORY CLE CE WE ALE RE tREAD I/O 0 ~ 7 90h Read ID Command 00h Address. 1cycle ECh Maker Code 79h Device Code A5h C0h Multi Plane Code ID Defintition Table 90 ID : Access command = 90H Value 1st Byte 2nd Byte 3rd Byte 4th Byte ECh 79h A5h C0h Description Maker Code Device Code Must be don't -cared Supports Multi Plane Operation (Must be don't-cared for 1.8V device) 28 Revision 1.0 June 2005 KBE00F005A-D411 Copy-Back Program Operation MCP MEMORY CLE CE tWC WE tWB tWB tPROG ALE tR RE I/O0~7 00h A0~A7 A9~A16 A17~A24 A25,A26 Column Address Page(Row) Address 8Ah A0~A7 A9~A16 A17~A24 A25,A26 Column Address Page(Row) Address 10h 70h I/O0 Read Status Command Busy Copy-Back Data Input Command I/O0=0 Successful Program I/O0=1 Error in Program 29 Busy Revision 1.0 June 2005 R/B KBE00F005A-D411 Device Operation PAGE READ MCP MEMORY Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 15s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each read operation. 30 Revision 1.0 June 2005 KBE00F005A-D411 Figure 8. Read1 Operation CLE CE WE ALE R/B RE I/O0~7 00h Start Add.(4Cycle) A0 ~ A7 & A9 ~ A26 (00h Command) 1st half array 2st half array MCP MEMORY tR Data Output(Sequential) (01h Command)* 1st half array 2st half array Data Field Spare Field Data Field Spare Field * After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 31 Revision 1.0 June 2005 KBE00F005A-D411 Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/O0~7 50h Start Add.(4Cycle) A0 ~ A3 & A9 ~ A26 (A4 ~ A7 : Dont Care) 1st half array 2nd half array MCP MEMORY tR Data Output(Sequential) Spare Field Data Field Spare Field 32 Revision 1.0 June 2005 KBE00F005A-D411 PAGE PROGRAM MCP MEMORY The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 10. Program & Read Status Operation R/B I/O0~7 80h Address & Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data tPROG 10h 70h I/O0 Pass Fail BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence. Figure 11. Block Erase Operation R/B I/O0~7 60h tBERS Address Input(3Cycle) Block Add. : A14 ~ A26 D0h 70h I/O0 Pass Fail 33 Revision 1.0 June 2005 KBE00F005A-D411 Multi-Plane Page Program into Plane 0~3 or Plane 4~7 MCP MEMORY Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7 enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane 4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited. Figure 12. Four-Plane Page Program R/B I/O0~7 80h tDBSY tDBSY tDBSY tPROG Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 11h 80h Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 11h 80h Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 11h 80h Address & 10h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 10h 71h Data input 80h 80h 80h 80h Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block) Block 0 Block 4 Block 1 Block 5 Block 2 Block 6 Block 3 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 Block 4091 Block 4095 34 Revision 1.0 June 2005 KBE00F005A-D411 Restirction in addressing with Multi Plane Page Program MCP MEMORY While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 13 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17. Figure 13. Multi-Plane Program & Read Status Operation Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block) Block 0 Page 0 Page 1 Block 1 Page 0 Page 1 Block 2 Page 0 Page 1 Block 3 Page 0 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Figure 14. Addressing Multiple Planes 80h Plane 2 11h 80h Plane 0 11h 80h Plane3 11h 80h Plane 1 10h Figure 15. Multi-Plane Page Program & Read Status Operation R/B I/O0~7 80h tPROG Last Plane input Address & Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 10h 71h I/O Pass Fail Multi-Plane Block Erase into Plane 0~3 or Plane 4~7 Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane. The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4). Figure 16. Four Block Erase Operation R/B I/O0~7 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) D0h tBERS 71h I/O Pass A0 ~ A7 & A9 ~ A26 Fail 35 Revision 1.0 June 2005 KBE00F005A-D411 Copy-Back Program MCP MEMORY The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14, A15 and A26 must be the same between source and target page. Figure20 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation. " Figure 17. One Page Copy-Back program Operation R/B I/O0~7 00h Add.(4Cycles) A0 ~ A7 & A9 ~ A26 Source Address tR tPROG 8Ah Add.(4Cycles) A0 ~ A7 & A9 ~ A26 Destination Address 10h 70h I/O0 Pass Fail 36 Revision 1.0 June 2005 KBE00F005A-D411 Multi-Plane Copy-Back Program MCP MEMORY Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted. First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished. Figure 18. Four-Plane Copy-Back Program Max Three Times Repeatable Source Address Input 00h 03h 03h 03h Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block) Block 0 Block 4 Block 1 Block 5 Block 2 Block 6 Block 3 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 Block 4091 Block 4095 Max Three Times Repeatable Destination Address Input 8Ah 11h 8Ah 11h 8Ah 11h 8Ah 10h Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block) Block 0 Block 4 Block 1 Block 5 Block 2 Block 6 Block 3 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 Block 4091 Block 4095 37 Revision 1.0 June 2005 Figure 19. Four-Plane Copy-Back Page Program (Continued) tR tR tR tDBSY tDBSY tPROG R/B 8Ah 11h 8Ah A0 ~ A7 & A9 ~ A25 Destination Address Add.(4Cyc.) Add.(4Cyc.) I/OX 03h Add.( 4Cyc.) Add.( 4Cyc.) 8Ah A0 ~ A7 & A9 ~ A25 Destination Address 03h Add.(4Cyc.) 11h 00h Add.(4Cyc.) 10h 71h KBE00F005A-D411 A0 ~ A7 & A9 ~ A25 Source Address A0 ~ A7 & A9 ~ A25 Source Address A0 ~ A7 & A9 ~ A25 Source Address A0 ~ A7 & A9 ~ A25 Destination Address tR : Normal Read Busy tDBSY : Typical 1us, Max 10us Max. 4 times ( 4 Cycle Source Address Input) repeatable Max. 4 times (4 Cycle Destination Address Input) repeatable 38 MCP MEMORY Revision 1.0 June 2005 KBE00F005A-D411 READ STATUS MCP MEMORY The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation. Table4. Read Staus Register Definition I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Status Total Pass/Fail Plane 0 Pass/Fail Plane 1 Pass/Fail Plane 2 Pass/Fail Plane 3 Pass/Fail Reserved Device Operation Write Protect Definition by 70h Command Pass : "0" Must be don't -cared Must be don't -cared Must be don't -cared Must be don't -cared Must be don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Fail : "1" Definition by 71h Command Pass : "0"(1) Pass : "0"(2) Pass : "0"(2) Pass : "0" (2) Fail : "1" Fail : "1" Fail : "1" Fail : "1" Fail : "1" Ready : "1" Not Protected : "1" Pass : "0"(2) Must be don't-cared Busy : "0" Protected : "0" NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/ Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane. 39 Revision 1.0 June 2005 KBE00F005A-D411 Read ID MCP MEMORY The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code*, Reserved(A5h), Multi plane operation code(C0h) respectively. A5h must be don't-cared. C0h means that device supports Multi Plane operation but must be don't-cared for 1.8V device. The command register remains in Read ID mode until further commands are issued to it. Figure 20 shows the operation sequence. Figure 20. Read ID Operation 1 CLE tCEA CE WE tAR ALE RE I/O0~7 90h 00h Address. 1cycle tWHR tREA ECh Maker code 79h Device code A5h C0h Multi-Plane code 40 Revision 1.0 June 2005 KBE00F005A-D411 RESET MCP MEMORY The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 21 below. Figure 21. RESET Operation R/B I/O0~7 FFh tRST Table5. Device Status After Power-up Operation Mode Read 1 After Reset Waiting for next command 41 Revision 1.0 June 2005 KBE00F005A-D411 READY/BUSY MCP MEMORY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 25). Its value can be determined by the following guidance. Rp VCC ibusy Ready Vcc R/B open drain output 0.4V, VOH : VccQ-0.4V VOH CL VOL Busy tf tr GND Device Figure 22. Rp vs tr ,tf & Rp vs ibusy @ Vcc = 2.7V, Ta = 25C , CL = 30pF tr,tf [s] 300n Ibusy 1.1 200n 100n 30 2m 90 0.75 2.3 120 tr 60 2.3 1m 2.3 0.55 2.3 tf 1K 2K 3K Rp(ohm) 4K Rp value guidance Rp(min, 2.7V part) = VCC(Max.) - VOL(Max.) IOL + IL = 2.5V 3mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr 42 Ibusy [A] 2.3 3m Revision 1.0 June 2005 KBE00F005A-D411 Data Protection & Power up sequence MCP MEMORY The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.8V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10s is required before internal circuit gets ready for any command sequences as shown in Figure 23. The two step command sequence for program/erase provides additional software protection. Figure 23. AC Waveforms for Power Transition ~ 2.0V VCC High ~ 2.0V WP WE 43 10s Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY 512Mb(16Mb x 32) Mobile SDRAM DDP F-Die 44 Revision 1.0 June 2005 KBE00F005A-D411 FUNCTIONAL BLOCK DIAGRAM MCP MEMORY CLK, /CAS, /RAS, /WE, DQM, CKE /CS1 8Mx32 8Mx32 /CS0 DQ0~DQ31 A0~A12, BA0, BA1 45 Revision 1.0 June 2005 KBE00F005A-D411 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 2.6 -1.0 ~ 2.6 -55 ~ +150 1.0 50 MCP MEMORY Unit V V C W mA NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD VDDQ VIH VIL VOH VOL ILI Min 1.7 1.7 0.8 x VDDQ -0.3 VDDQ -0.2 -2 Typ 1.8 1.8 1.8 0 Max 1.95 1.95 VDDQ + 0.3 0.3 0.2 2 Unit V V V V V V uA 1 2 IOH = -0.1mA IOL = 0.1mA 3 Note NOTES : 1. VIH (max) = 2.2V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -1.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V VOUT VDDQ. CAPACITANCE (VDD = 1.8V, TA = 23C, f = 1MHz, VREF =0.9V 50 mV) Pin Clock CS RAS, CAS, WE, CKE DQM Address DQ0 ~ DQ31 Symbol CCLK CIN CIN CIN CADD COUT Min 2.5 1.5 2.5 2.5 2.5 5 Max 6 3 6 6 6 10 Unit pF pF pF pF pF pF Note 46 Revision 1.0 June 2005 KBE00F005A-D411 DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85C) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tARFC tARFC(min) TCSR Range Self Refresh Current ICC6 CKE 0.2V Full Array 1/2 of Full Array 1/4 of Full Array Test Condition MCP MEMORY KBE00F005A-D411 111MHz@CL3 50 0.6 0.6 20 Unit Note ICC1 ICC2P ICC2PS ICC2N mA 1 mA Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N ICC3NS mA 2 6 2 30 6 mA mA mA Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current ICC4 90 mA 1 ICC5 70 Max 40 300 240 200 Max 85 800 600 500 mA C 2 uA NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ). 4. Measued with assumption that one of the 2 die should be in a state of Precharge standby in non power-down mode. 47 Revision 1.0 June 2005 KBE00F005A-D411 AC OPERATING TEST CONDITIONS(VDD = 1.7V 1.95V, TA = Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition -25 to 85C) MCP MEMORY Value 0.9 x VDDQ / 0.2 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Figure 2 Unit V V ns V 1.8V 13.9K Output 10.6K VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA VOL (DC) = 0.2V, IOL = 0.1mA 20pF Output Z0=50 Vtt=0.5 x VDDQ 50 20pF Figure 1. DC Output Load Circuit Figure 2. AC Output Load Circuit 48 Revision 1.0 June 2005 KBE00F005A-D411 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Auto refresh cycle time Exit self refresh to active command Col. address to col. address delay Number of valid output data Number of valid output data Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tARFC(min) tSRFX(min) tCCD(min) CAS latency=3 CAS latency=2 CAS latency=1 KBE00F005A-D411 111MHz@CL3 18 27 27 50 100 77 15 tRDL + tRP 1 1 80 120 1 2 1 0 MCP MEMORY Unit ns ns ns ns us ns ns CLK CLK ns ns CLK Note 1 1 1 1 1 2 2 2 3 ea 4 NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 49 Revision 1.0 June 2005 KBE00F005A-D411 AC CHARACTERISTICS(AC operating conditions unless otherwise noted) Parameter Symbol MCP MEMORY KBE00F005A-D411 111MHz@CL3 Min Max Unit Note CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 tCC tCC tCC tSAC tSAC tSAC tOH tOH tOH tCH tCL tSS tSH tSLZ 9 15 25 7 10 20 2.0 2.0 2.0 3.0 3.0 2.0 1.5 1 7 ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1,2 1000 ns 1 tSHZ 10 20 ns NOTES : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, 50 Revision 1.0 June 2005 KBE00F005A-D411 SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn H H X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H MCP MEMORY DQM BA0,1 A10/AP X X A12,A11, Note A9 ~ A0 1, 2 3 3 3 3 OP CODE X L H H X X X V V X Row Address L H L H X V X L H X Column Address (A0~A7) Column Address (A0~A7) Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command 4 4, 5 4 4, 5 6 H H H X X X L L L H L X H L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V X X X V Clock Suspend or Active Power Down H L H L H L X X X X X X V X X 7 L H H H X H L X H X H X H X (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) NOTES : 1. OP Code : Operand Code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). 51 Revision 1.0 June 2005 KBE00F005A-D411 A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address Function BA0 ~ BA1 "0" Setting for Normal MRS A12 ~ A10/AP RFU*1 A9*2 W.B.L A8 A7 A6 A5 A4 MCP MEMORY A3 BT A2 A1 Burst Length A0 Test Mode CAS Latency Normal MRS Mode Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 0 Setting for Normal MRS A3 0 1 Burst Type Type Sequential Interleave Mode Select BA1 BA0 Mode A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 Reserved Reserved Reserved Full Page BT=1 1 2 4 8 Reserved Reserved Reserved Reserved Write Burst Length A9 0 1 Length Burst Single Bit Full Page Length x32 : 512Mb(512) Register Programmed with Extended MRS Address Function BA1 BA0 A12 ~ A10/AP A9 RFU*1 A8 A7 A6 DS A5 A4 A3 A2 A1 PASR A0 Mode Select RFU*1 EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength) Mode Select BA1 0 0 1 1 BA0 0 1 0 1 Mode Normal MRS Reserved EMRS for Mobile SDRAM Reserved Reserved Address A12~A10/AP 0 A9 0 A8 0 A7 0 A4 0 A3 0 A6 0 0 1 1 Driver Strength A5 0 1 0 1 Driver Strength Full 1/2 1/4 1/8 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 PASR Size of Refreshed Area Full Array 1/2 of Full Array 1/4 of Full Array Reserved Reserved Reserved Reserved Reserved NOTES: 1.RFU(Reserved for future use) should stay "0" during MRS cycle. 2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 52 Revision 1.0 June 2005 KBE00F005A-D411 Partial Array Self Refresh MCP MEMORY 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array, 1/4 of Full Array BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 - Full Array - 1/2 Array - 1/4 Array Partial Self Refresh Area Internal Temperature Compensated Self Refresh (TCSR) Note : 1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range ; Max. 40 C, Max. 85 C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Self Refresh Current (Icc 6) Temperature Range Full Array Max. 40 C Max. 85 C 300 800 1/2 of Full Array 240 600 1/4 of Full Array 200 500 uA Unit B. POWER UP SEQUENCE 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the half driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. 53 Revision 1.0 June 2005 KBE00F005A-D411 C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 Sequential 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 MCP MEMORY Interleave 2 3 0 1 3 2 1 0 2. BURST LENGTH = 8 Initial Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 54 Revision 1.0 June 2005 KBE00F005A-D411 D. DEVICE OPERATIONS ADDRESSES of 512Mb BANK ADDRESSES (BA0 ~ BA1) This SDRAM is organized as two chips which has four independent banks of 2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations. MCP MEMORY CLOCK (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications. CLOCK ENABLE (CKE) ADDRESS INPUTS (A0 ~ A12) The 21 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (A0 ~ A12). The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses (A0 ~ A7) are latched along with CAS, WE and BA0 ~ BA1 during read or write command. The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. NOP and DEVICE DESELECT When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. 55 Revision 1.0 June 2005 KBE00F005A-D411 D. DEVICE OPERATIONS (continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also. MCP MEMORY EXTENDED MODE REGISTER SET (EMRS) The extended mode register stores the data for selecting driver strength, partial self refresh or temperature compensated self refresh. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is half driver strength, and all 4 banks refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 - A2 are used for partial self refresh , A5 - A6 are used for Driver strength, "Low" on BA1 and "High" on BA0 are used for EMRS. All the other address pins except A0-A2, A5-A6 and BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP ~ An and BA0 ~ BA1. The write burst length is programmed using A9. A7 ~ A8, A10/AP ~ An and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. BANK ACTIVATE. The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. 56 Revision 1.0 June 2005 KBE00F005A-D411 D. DEVICE OPERATIONS (continued) The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification. MCP MEMORY BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. ALL BANKS PRECHARGE All banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge to all the banks, all banks are in idle state. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. PRECHARGE The precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. 57 Revision 1.0 June 2005 KBE00F005A-D411 D. DEVICE OPERATIONS (continued) AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. MCP MEMORY SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tSRFX before the SDRAM reaches idle state to begin normal operation. In case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096 auto refresh cycles for 128Mb and 64Mb immediately before entering self refresh mode and after exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle. AUTO REFRESH The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRC(min). The minimum number of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The 64Mb and 128Mb SDRAM's auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. The 256Mb and 512Mb SDRAM's auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms. 58 Revision 1.0 June 2005 KBE00F005A-D411 E. BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write CLK CMD CKE Internal CLK DQ(CL2) DQ(CL3) D0 D0 D1 D1 D2 D2 D3 D3 WR Masked by CKE MCP MEMORY 2) Clock Suspended During Read (BL=4) CLK CMD CKE Internal CLK DQ(CL2) DQ(CL3) Q0 D Q1 Q0 Q2 Q1 Q3 Q2 Q3 RD Masked by CKE Not Written Suspended Dout 2. DQM Operation 1) Write Mask (BL=4) CLK CMD DQM Masked by CKE 2) Read Mask (BL=4) CLK WR CMD DQM RD Masked by CKE Hi-Z DQ(CL2) DQ(CL3) D0 D0 D1 D1 D3 D3 DQ(CL2) DQ(CL3) Q0 Q2 Q3 Q2 Hi-Z Q1 Q3 DQM to Data-in Mask = 0 3) DQM with Clock Suspended (Full Page Read) *2 CLK CMD CKE DQM DQ(CL2) DQ(CL3) Q0 Hi-Z Hi-Z DQM to Data-out Mask = 2 RD Q2 Q1 Hi-Z Hi-Z Q4 Q3 Hi-Z Hi-Z Q6 Q5 Q7 Q6 Q8 Q7 *NOTE : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. 59 Revision 1.0 June 2005 KBE00F005A-D411 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) *1 CLK CMD ADD DQ(CL2) DQ(CL3) tCCD *2 MCP MEMORY RD A RD B QA0 QB0 QB1 QB1 QB3 QA0 QB0 QB1 QB1 QB3 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD *2 3) Write interrupted by Read (BL=2) CLK CMD ADD DQ(CL2) DQ(CL3) WR A DA0 DA0 RD B QB0 QB1 QB0 QB1 tCCD *2 ADD DQ A B DA0 DB0 DB1 tCDL *3 tCDL *3 *NOTE: 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) 60 Revision 1.0 June 2005 KBE00F005A-D411 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (b) CL=3, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ v) CMD DQM DQ Q0 Hi-Z *1 MCP MEMORY RD WR D0 RD D1 WR D2 D3 Hi-Z D0 D1 WR D2 D3 RD Hi-Z D0 D1 WR D2 D3 RD Q0 Hi-Z *1 D0 D1 D2 D3 RD WR D0 RD D1 WR D2 D3 D0 RD D1 WR D2 D3 D0 RD D1 WR D2 D3 Hi-Z D0 D1 WR D2 D3 RD D0 D1 D2 D3 *NOTE: 1. To prevent bus contention, there should be at least one gap between data in and data out. 61 Revision 1.0 June 2005 KBE00F005A-D411 5. Write Interrupted by Precharge & DQM 1) tRDL = 2CLK CLK CMD DQM DQ D0 D1 D2 Masked by DQM MCP MEMORY WR PRE *3 *2 *NOTE: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 6. Precharge 1) Normal Write BL=4 & tRDL=2CLK CLK CMD DQ WR D0 D1 D2 D3 tRDL*1 PRE 2) Normal Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 PRE Q2 Q1 *2 Q3 Q2 1 Q3 2 7. Auto Precharge 1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3 tRDL =2CLK tDAL =tRDL + tRP*4 Auto Precharge Starts *3 Auto Precharge Starts@tRDL=2CLK *3 2) Normal Read (BL=4) CLK ACT CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 Q2 Q1 Q3 Q2 Q3 *NOTE: 1. SAMSUNG can support tRDL=2CLK . 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal 4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP . 62 Revision 1.0 June 2005 KBE00F005A-D411 8. Burst Stop & Interrupted by Precharge 1) Normal Write BL=4 & tRDL=2CLK CLK CMD DQM DQ D0 D1 D2 tRDL*1 MCP MEMORY WR PRE 2) Write Burst Stop (BL=8) CLK CMD DQM DQ D0 D1 D2 D3 tBDL *2 3) Read Interrupted by Precharge (BL=4) CLK WR STOP CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0 1 Q1 2 4) Read Burst Stop (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD STOP Q0 Q1 Q0 1 Q1 2 9. MRS 1) Mode Register Set CLK *4 CMD PRE tRP MRS 2CLK ACT *NOTE: 1. SAMSUNG can support tRDL=2CLK. 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively. 4. PRE : All banks precharge is necessary. MRS can be issued only at all banks precharge state. 63 Revision 1.0 June 2005 KBE00F005A-D411 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal CLK CMD *1 MCP MEMORY 2) Power Down (=Precharge Power Down) Exit CLK tSS CKE Internal CLK RD CMD *2 tSS NOP ACT 11. Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tARFC(min). Command CKE = High PRE Auto Refresh CLK CMD tRP(min) tARFC(min) Self Refresh A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including system clock(CLK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle. CLK Command CKE tSS Self Refresh Stable Clock NOP ACT tSS 64 tSRFX(min) Revision 1.0 June 2005 KBE00F005A-D411 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random MODE Random column Access tCCD = 1 CLK MCP MEMORY At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting. Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "010". At MRS A2,1,0 = "011". At MRS A2,1,0 = "111". Wrap around mode(infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt. At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1. At auto precharge of write, tRAS should not be violated. tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. Special MODE Random MODE BRSW Burst Stop RAS Interrupt (Interrupted by Precharge) Interrupt MODE CAS Interrupt 65 Revision 1.0 June 2005 KBE00F005A-D411 FUNCTION TRUTH TABLE (TABLE 1) Current State CS H L L IDLE L L L L L H L L Row Active L L L L L H L L Read L L L L L H L L Write L L L L L H Read with Auto Precharge L L L L L H Write with Auto Precharge L L L L L RAS X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L CAS X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L WE X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X BA X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X Address X X X RA A10/AP X OP code X X X NOP NOP ILLEGAL Action MCP MEMORY Note 2 2 4 5 5 CA, A10/AP ILLEGAL Row (& Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL 2 CA, A10/AP Begin Read ; latch CA ; determine AP CA, A10/AP Begin Read ; latch CA ; determine AP RA A10/AP X X X X ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active 3 2 2 CA, A10/AP Term burst, New Read, Determine AP CA, A10/AP Term burst, New Write, Determine AP RA A10/AP X X X X ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active 3 3 2 3 CA, A10/AP Term burst, New read, Determine AP CA, A10/AP Term burst, New Write, Determine AP RA A10/AP X X X X RA, RA10 X X X X RA, RA10 X ILLEGAL Term burst, precharge timing for Writes ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL CA, A10/AP ILLEGAL 2 CA, A10/AP ILLEGAL 2 66 Revision 1.0 June 2005 KBE00F005A-D411 FUNCTION TRUTH TABLE (TABLE 1) Current CS H L Precharging L L L L L H L Row Activating L L L L L H L Refreshing L L L H Mode Register Accessing L L L L RAS X H H H L L L X H H H L L L X H H L L X H H H L CAS X H H L H H L X H H L H H L X H L H L X H H L X WE X H L X H L X X H L X H L X X X X X X X H L X X BA X X X BA BA BA X X X X BA BA BA X X X X X X X X X X X Address X X X CA RA A10/AP X X X X CA RA A10/AP X X X X X X X X X X X MCP MEMORY Action NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after tRP ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after 2 clocks NOP --> Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL Note 2 2 2 4 2 2 2 2 Abbreviations : RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address AP = Auto Precharge *NOTE: 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. 67 Revision 1.0 June 2005 KBE00F005A-D411 FUNCTION TRUTH TABLE (TABLE 2) Current State CKE (n-1) H L Self Refresh L L L L L H All Banks Precharge Power Down L L L L L L H H H All Banks Idle H H H H H L Any State other than Listed above H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X H H L X X X X X Address X X X X X X X X X X X X X X X X X X X RA X X X X X X MCP MEMORY Action Exit Self Refresh --> Idle after tsRFX(ABI) Exit Self Refresh --> Idle after tsRFX (ABI) Exit Self Refresh --> Idle after tsRFX (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active Enter Self Refresh NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Note 6 6 7 7 8 8 8 OP Code Mode Register Access 9 9 Abbreviations : ABI = All Banks Idle, RA = Row Address *NOTE: 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the all banks idle state. 9. Must be a legal command. 68 Revision 1.0 June 2005 KBE00F005A-D411 Power Up Sequence Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read & Write Cycle at Different Bank @Burst Length=4 Read & Write Cycle With Auto Precharge l @Burst Length=4 Read & Write Cycle With Auto Precharge ll @Burst Length=4 Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK Burst Read Single bit Write Cycle @Burst Length =2 Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry & Exit Cycle & Exit Cycle Mode Register Set Cycle and Auto Refresh Cycle Extended Mode Register Set Cycle MCP MEMORY 69 Revision 1.0 June 2005 KBE00F005A-D411 Power Up Sequence for Mobile SDRAM 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CKE Hi CS RAS CAS ADDR Key Key RAa BA0 BA1 A10/AP RAa DQ Hi-Z Hi-Z WE DQM High level is necessary tRP Precharge (All Bank) Auto Refresh tARFC Auto Refresh tARFC Normal MRS Extended MRS Row Active (A-Bank) : Don't care *NOTE: 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the half driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. 70 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 0 CLOCK 1 2 tCC 3 tCH 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tCL tRAS tRC HIGH tSH tSS tRP CKE *Note 1 CS tRCD tSH RAS tSS CAS tSH tSH tSS Ca *Note 2,3 ADDR Ra *Note 2 Cb *Note 2,3 Cc *Note 2,3 *Note 4 Rb *Note 2 tSS BA0,BA1 BS BS *Note 3 BS *Note 3 BS *Note 3 BS *Note 4 BS A10/AP Ra Rb tSAC DQ Qa tSH Db Qc tSLZ WE tOH tSS tSS tSH tSS tSH DQM Row Active Read Write Read Precharge Row Active : Don't care *NOTE: 1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0,BA1. 71 Revision 1.0 June 2005 KBE00F005A-D411 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH tRC *Note 1 CS RAS *Note 2 CAS ADDR Ra Ca Rb Cb BA0 BA1 A10/AP Ra Rb DQ { tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 CL=2 tRCD tSAC Qa0 tSHZ tOH Qa1 Qa2 Qa3 *Note 4 tRDL Db0 Db1 Db2 Db3 CL=3 tSAC WE tSHZ *Note 4 tRDL DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *NOTE: 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok. 3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) 72 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS *Note 2 CAS ADDR Ra Ca Cb Cc Cd Rb BA0 BA1 A10/AP Ra Rb tRDL DQ { CL=2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 tRCD Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 tDAL *Note 4 CL=3 tCDL WE *Note 1 *Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) Row Active (A-Bank) : Don't care *NOTE: 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL ,last data in to active delay, is 2CLK + tRP. 73 Revision 1.0 June 2005 KBE00F005A-D411 Page Read Cycle at Different Bank @Burst Length=4 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE *Note 1 HIGH CS RAS *Note 2 CAS ADDR RAa RBb CAa RCc CBb RDd CCc CDd BA0 BA1 A10/AP RAa RBb RCc RDd DQ { CL=2 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 CL=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Row Active (C-Bank) Read (C-Bank) Row Active (D-Bank) Read (D-Bank) Precharge (C-Bank) Precharge (D-Bank) Precharge (A-Bank) Precharge (B-Bank) : Don't care *NOTE: 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. 74 Revision 1.0 June 2005 KBE00F005A-D411 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS *Note 2 CAS ADDR RAa RAb CAa CBb RCc RDd CCc CDd BA0 BA1 A10/AP RAa RBb RCc RDd DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2 tCDL WE *Note 1 tRDL DQM Row Active (A-Bank) Write (A-Bank) Row Active (B-Bank) Write (B-Bank) Row Active (C-Bank) Row Active (D-Bank) Write (C-Bank) Write (D-Bank) Precharge (All Banks) : Don't care *NOTE: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. 75 Revision 1.0 June 2005 KBE00F005A-D411 Read & Write Cycle at Different Bank @Burst Length=4 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR RAa CAa RDb CDb RBc CBc BA0 BA1 A10/AP RAa RDb RBc tCDL DQ { *Note 1 CL=2 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QBc0 QBc1 QBc2 CL=3 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QBc0 QBc1 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (D-Bank) Write (D-Bank) Row Active (B-Bank) Read (B-Bank) : Don't care *NOTE: 1. tCDL should be met to complete write. 76 Revision 1.0 June 2005 KBE00F005A-D411 Read & Write Cycle with Auto Precharge I @Burst Length=4 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR RAa RBb CAa CBb RAc CAc BA0 BA1 A10/AP RAa RBb RAc DQ CL=2 QAa0 QAa1 QBb0 QBb1 QBb2 DBb3 DAc0 DAc1 CL=3 QAa0 QAa1 QBb0 QBb1 QBb2 DBb3 DAc0 DAc1 WE DQM Row Active (A-Bank) Read with Auto Pre charge (A-Bank) Row Active (B-Bank) Read without Auto Precharge(B-Bank) Auto Precharge Start Point (A-Bank) *Note1 Precharge (B-Bank) Row Active (A-Bank) Write with Auto Precharge (A-Bank) : Don't care *NOTE: 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start at B-Bank read command input point . - any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts. 77 Revision 1.0 June 2005 KBE00F005A-D411 Read & Write Cycle with Auto Precharge II @Burst Length=4 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR Ra Ca Rb Cb BA0 BA1 A10/AP Ra Rb DQ CL=2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 CL=3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 WE DQM *Note1 Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Row Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care *NOTE: 1. Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point 78 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS RAS CAS ADDR Ra Ca Cb Cc BA0 BA1 A10/AP Ra DQ Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Dc0 Dc2 tSHZ WE tSHZ *Note 1 DQM Row Active Read Clock Suspension Read Read DQM Write Write DQM Clock Suspension Write DQM : Don't care *NOTE: 1. DQM is needed to prevent bus contention. 79 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA0 BA1 A10/AP RAa 1 1 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 DQ { CL=2 QAa0 QAa1 QAa2 QAa3 QAa4 2 CL=3 QAa0 QAa1 QAa2 QAa3 QAa4 2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) : Don't care *NOTE: 1. At full page mode, burst is finished by burst stop or precharge. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. 80 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA0 BA1 A10/AP RAa *Note 1 tBDL *Note 1,2 tRDL DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care *NOTE: 1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. 81 Revision 1.0 June 2005 KBE00F005A-D411 Burst Read Single bit Write Cycle @Burst Length=2 0 CLOCK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS *Note 2 CAS ADDR RAa CAa RBb CAb RCc CBc CCd BA0 BA1 A10/AP RAa RBb RCc DQ { CL=2 DAa0 QAb0 QAb1 DBc0 QCd0 QCd1 CL=3 DAa0 QAb0 QAb1 DBc0 QCd0 QCd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Read with (A-Bank) Auto Precharge (A-Bank) Row Active (C-Bank) Write with Auto Precharge (B-Bank) Read (C-Bank) Precharge (C-Bank) : Don't care *NOTE: 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. 82 Revision 1.0 June 2005 KBE00F005A-D411 MCP MEMORY Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tSS CKE *Note 1 tSS *Note 2 tSS *Note 2 *Note 3 CS RAS CAS ADDR Ra Ca BA A10/AP Ra DQ Qa0 Qa1 Qa2 tSHZ WE DQM Precharge Power-down Entry Row Active Precharge Power-down Exit Active Power-down Entry Active Power-down Exit Read Precharge : Don't care *NOTE: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command. 3. Can not violate minimum refresh specification. (64ms) 83 Revision 1.0 June 2005 KBE00F005A-D411 Self Refresh Entry & Exit Cycle 0 CLOCK *Note 2 *Note 1 MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note 4 tSRFX *Note 6 CKE *Note 3 tSS CS RAS CAS ADDR BA0,BA1 A10/AP DQ Hi-Z Hi-Z WE DQM Self Refresh Entry Self Refresh Exit Auto Refresh : Don't care *NOTE: TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tSRFX is required after CKE going high to complete self refresh exit. 7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb, 512Mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. 84 Revision 1.0 June 2005 KBE00F005A-D411 Mode Register Set Cycle 0 CLOCK MCP MEMORY Auto Refresh Cycle 5 6 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 CKE HIGH HIGH CS *Note 2 tARFC RAS *Note 1 CAS *Note 3 ADDR Key Ra BA0 BA1 DQ Hi-Z Hi-Z WE DQM MRS New Command Auto Refresh New Command * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. : Don't care *NOTE: MODE REGISTER SET CYCLE 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. 85 Revision 1.0 June 2005 KBE00F005A-D411 Extended Mode Register Set Cycle 0 CLOCK MCP MEMORY 1 2 3 4 5 6 CKE HIGH CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra BA0 BA1 DQ Hi-Z WE DQM EMRS New Command : Don't care *NOTE: EXTENDED MODE REGISTER SET CYCLE 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. 86 Revision 1.0 June 2005 KBE00F005A-D411 PACKAGE DIMENSION MCP MEMORY 137-Ball Fine pitch Ball Grid Array Package (measured in millimeters) Units:millimeters #A1 INDEX MARK 0.10 MAX 10.500.10 (Datum A) 0.80x9=7.20 10 9 8 7 6 5 4 3 2 1 A B C D (Datum B) E F G H J K L M N P R 5.60 0.80 10.500.10 A B #A1 0.450.05 0.80 0.320.05 1.300.10 TOP VIEW 137-0.450.05 0.20 M A B 3.60 BOTTOM VIEW 87 Revision 1.0 June 2005 0.80x14=11.20 13.000.10 13.000.10 13.000.10 |
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